As technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate feature with a metal gate feature to improve device performance with the decreased feature sizes. One process of forming a metal gate feature is termed a “gate last” process in which the final gate feature is fabricated “last” which allows for a reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate.
However, there are challenges to implement such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, non-uniform distribution of metal gate features causes loading effects during an etching process and/or a chemical-mechanical polishing (CMP) process, thereby increasing the likelihood of device instability and/or device failure.